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FINAL
COM'L: H-7/10/15/20
IND: H-10/15/20
PALCE26V12 Family
28-Pin EE CMOS Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
s 28-pin versatile PAL programmable logic device architecture s Electrically erasable CMOS technology provides half power (only 115 mA) at high speed (7.5 ns propagation delay) s 14 dedicated inputs and 12 input/output macrocells for architectural flexibility s Macrocells can be registered or combinatorial, and active high or active low s Varied product term distribution allows up to 16 product terms per output s Two clock inputs for independent functions s Global asynchronous reset and synchronous preset for initialization s Register preload for testability and built-in register reset on power-up s Space-efficient 28-pin SKINNYDIP and PLCC packages s Center VCC and GND pins to improve signal characteristics s Extensive third-party software and programmer support through FusionPLD partners
GENERAL DESCRIPTION
The PALCE26V12 is a 28-pin version of the popular PAL22V10 architecture. Built with low-power, highspeed, electrically-erasable CMOS technology, the PALCE26V12 offers many unique advantages. Device logic is automatically configured according to the user's design specification. Design is simplified by design software, allowing automatic creation of a programming file based on Boolean or state equations. The software can also be used to verify the design and can provide test vectors for the programmed device. The PALCE26V12 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The functions are programmed into the device through electrically-erasable floating-gate cells in the AND logic array and the macrocells. In the unprogrammed state, all AND product terms float HIGH. If both true and complement of any input are connected, the term will be permanently LOW. The product terms are connected to the fixed OR array with a varied distribution from 8 to 16 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial, active high or active low, with registered I/O possible. The flip-flop can be clocked by one of two clock inputs. The output configuration is determined by four bits controlling three multiplexers in each macrocell. AMD's FusionPLD program allows PALCE26V12 designs to be implemented using a wide variety of popular industry-standard design tools. By working closely with the FusionPLD partners, AMD certifies that the tools provide accurate, quality support. By ensuring that third-party tools are available, costs are lowered because a designer does not have to buy a complete set of new tools for each device. The FusionPLD program also greatly reduces design time since a designer can use a tool that is already installed and familiar. Please refer to the PLD Software Reference Guide for certified development systems and the Programmer Reference Guide for approved programmers.
2-306
Publication# 16072 Rev. E Issue Date: February 1996
Amendment /0
AMD
BLOCK DIAGRAM
CLK/I 2 12 I
SYNC. PRESET 8 8 10 12 14
PROGRAMMABLE AND ARRAY (52x150) 16 16 14 12 10 8 8
ASYNC. RESET
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
16072E-1
CONNECTION DIAGRAMS Top View DIP
CLK2/I3 CLK1/I0 I1 I2 CLK2/I3 I4 I5 VCC I6 I7 I8 I9 I10 I11 I12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 I13 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 GND I/O5 I/O4 I/O3 I/O2 I/O1 I4 I5 VCC I6 I7 I8 I9 5 6 7 8 9 10 11 4 3
PLCC
CLK1/I0 I/O11 I/O10
I1
2
1 28 27 26 25 24 23 22 21 20 19 I/O9 I/O8 I/O7 I/O6 GND I/O5 I/O4
12 13 14 15 16 17 18 I/O0 I/O1 I/O2 I/O3 I10 I11 I12
I/O0
16072E-2
Note: Pin 1 is marked for orientation.
I13
I2
16072E-3
PIN DESCRIPTION
CLK GND I I/O VCC = = = = = Clock Ground Input Input/Output Supply Voltage PALCE26V12 Family 2-307
AMD
ORDERING INFORMATION Commercial and Industrial Products
AMD commercial and industrial programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL CE 26 V 12 H -7 P C /4
FAMILY TYPE PAL = Programmable Array Logic TECHNOLOGY CE = CMOS Electrically Erasable NUMBER OF ARRAY INPUTS OUTPUT TYPE V = Versatile NUMBER OF OUTPUTS POWER H= Half Power (115 mA ICC)
OPTIONAL PROCESSING Blank = Standard Processing PROGRAMMING DESIGNATOR /4 = First Revision (May require programmer update) OPERATING CONDITIONS C = Commercial (0C to +75C) I = Industrial (-40C to +85C) PACKAGE TYPE P = 28-Pin 300 mil Plastic SKINNYDIP (PD3028) J = 28-Pin Plastic Leaded Chip Carrier (PL 028) SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD
Valid Combinations PALCE26V12H-7 PALCE26V12H-10 PALCE26V12H-15 PALCE26V12H-20 JC PC, JC, PI, JI /4
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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PALCE26V12H-7/10/15/20 (Com'l), H-10/15/20 (Ind)
AMD
FUNCTIONAL DESCRIPTION
The PALCE26V12 has fourteen dedicated input lines, two of which can be used as clock inputs. Unused inputs should be tied directly to ground or VCC. Buffers for device inputs and feedbacks have both true and complementary outputs to provide user-selectable signal polarity. The inputs drive a programmable AND logic array, which feeds a fixed OR logic array. The OR gates feed the twelve I/O macrocells (see Figure 1). The macrocell allows one of eight potential output configurations; registered or combinatorial, active high or active low, with register or I/O pin feedback (see Figure 2). In addition, registered configurations can be clocked by either of the two clock inputs. The configuration choice is made according to the user's design specification and corresponding programming of the configuration bits S0-S3 (see Table 1). Multiplexer controls initially float to VCC (1) through a programmable cell, selecting the "1" path through the multiplexer. Programming the cell connects the control line to GND (0), selecting the "0" path.
OE AR CLK 1 P1 AR DQ 1 0 CLK 2 SP 1 S3* S2 0 S1 Q SP 1 1 0 0 0 1 0 1 S0
Pn
n = 8,8,10,12,14,16
* When S 3 = 1 (unprogrammed) the feedback is selected by S 1. When S 3 = 0 (programmed), the feedback is the opposite of that selected by S 1.
16072E-4
Figure 1. PALCE26V12 Macrocell
Registered or Combinatorial
Each macrocell of the PALCE26V12 includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH edge of the selected clock input. Any macrocell can be configured as combinatorial by selecting a multiplexer path that bypasses the flip-flop. Bypass is controlled by bit S1.
Table 1. Macrocell Configuration Table
S3 1 1 1 1 0 0 0 0 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Output Configuration Registered Output and Feedback, Active Low Registered Output and Feedback, Active High Combinatorial I/O, Active Low Combinatorial I/O, Active High Registered I/O, Active Low Registered I/O, Active High Combinatorial Output, Registered Feedback, Active Low Combinatorial Output, Registered Feedback, Active High
Programmable Clock
The clock input for any flip-flop can be selected to be from either pin 1 or pin 4. A 2:1 multiplexer controlled by bit S2 determines the clock input.
Programmable Feedback
A 2:1 multiplexer allows the user to determine whether the macrocell feedback comes from the flip-flop or from the I/O pin, independent of whether the output is registered or combinatorial. Thus, registered outputs may have internal register feedback for higher speed (fMAX internal), or I/O feedback for use of the pin as a direct input (fMAX external). Combinatorial outputs may have I/O feedback, either for use of the signal in other equations or for use as another direct input, or register feedback.
1 = Unprogrammed EE bit 0 = Programmed EE bit
S2 1 0 Clock Input CLK1/I0 CLK2/I3
PALCE26V12 Family
2-309
AMD The feedback multiplexer is controlled by the same bit (S1) that controls whether the output is registered or combinatorial, as on the 22V10, with an additional control bit (S3) that allows the alternative feedback path to be selected. When S3 = 1, S1 selects register feedback for registered outputs (S1 = 0) and I/O feedback for combinatorial outputs (S1 = 1). When S3 = 0, the opposite is selected: I/O feedback for registered outputs and register feedback for combinatorial outputs.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE26V12 will be HIGH or LOW depending on whether the output is active low or active high, respectively. The VCC rise must be monotonic, and the reset delay time is 1000 ns maximum.
Register Preload
The register on the PALCE26V12 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, thereby making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery.
Programmable Enable and I/O
Each macrocell has a three-state output buffer controlled by an individual product term. Enable and disable can be a function of any combination of device inputs or feedback. The macrocell provides a bidirectional I/O pin if I/O feedback is selected, and may be configured as a dedicated input if the buffer is always disabled. This is accomplished by connecting all inputs to the enable term, forcing the AND of the complemented inputs to be always LOW. To permanently enable the outputs, all inputs are left disconnected from the term (the unprogrammed state).
Security Bit
After programming and verification, a PALCE26V12 design can be secured by programming the security bit. Once programmed, this bit defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. Programming the security bit disables preload, and the array will read as if every bit is disconnected. The security bit can only be erased in conjunction with erasure of the entire pattern.
Programmable Output Polarity
The polarity of each macrocell output can be active high or active low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save "DeMorganizing" efforts. Selection is controlled by programmable bit S0 in the output macrocell, and affects both registered and combinatorial outputs. Selection is automatic, based on the design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be active high.
Programming and Erasing
The PALCE26V12 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming hardware. No special erase operation is required.
Quality and Testability
The PALCE26V12 offers a very high level of built-in quality. The erasability of the device provides a means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry.
Preset/Reset
For initialization, the PALCE26V12 has additional Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous Preset (SP) product term is asserted high, the output registers will be loaded with a HIGH or the next LOW-to-HIGH clock transition. When the Asynchronous Reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW independent of the clock. Note that preset and reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected.
Technology
The high-speed PALCE26V12 is fabricated with AMD's advanced electrically erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching.
2-310
PALCE26V12 Family
AMD
D CLK
AR
Q CLK
D
AR
Q
SP Q
SP Q
Registered Active-Low Output, Register Feedback
Registered Active-High Output, Register Feedback
D CLK
AR
Q CLK
D
AR
Q
SP Q
SP Q
Registered Active-Low I/O
Registered Active-High I/O
Registered Outputs
Combinatorial Active-Low I/O
Combinatorial Active-High I/O
D CLK
AR
Q CLK
D
AR
Q
SP Q
SP Q
Combinatorial Active-Low Output, Register Feedback
Combinatorial Active-High Output, Register Feedback
Combinatorial Outputs
16072E-5
Figure 2. PALCE26V12 Macrocell Configuration Options PALCE26V12 Family 2-311
AMD
LOGIC DIAGRAM
PALCE26V12
0 0 4 8 12 16 20 24 28 32 36 40 44 48
ASYNCH. RESET
1
1
28 I 13
10 AR 11 Q Q SP S2 00 01 S0 S1 0 1 S3 * R 11 D 1
CLK 1 /I 0
27 I/O 11
9
0
2 I1
10
10 11 D 1 18 0 S2 Q SP R S0 S1 10 AR Q 00 01
26 I/O 10
3 I2
19
0 1
S3 *
D ARQ 1 0
29
10 11 00 01 S0 S1
SP S2
Q
25 I/O 9
4 CLK 2 /I 3
30
0 1
R9 S3*
D ARQ 1 0
42
10 11 00 01 S0 R8 S3 * S1
SP S2
Q
24 I/O 8
5 I4
43
0 1
D ARQ 1 0 S2
57
SP
Q
10 11 00 01 S0 S1
23 I/O 7
6 I5
58
0 1
R7 S3 *
D ARQ 1 0 S2
74
Q SP R6 S3 *
10 11 00 01 S0 S1
22 I/O 6
8 I6
0 1
0 4 8 12 16 20 24 28 32 36 40 44 48
AR CLK1 SP CLK 2
* When S 3 = 1 (unprogrammed) the feedback is selected by S1. When S 3 = 0 (programmed), the feedback is the opposite of that selected by S1.
21 GND
16072E-6
2-312
PALCE26V12 Family
AMD
LOGIC DIAGRAM (continued)
PALCE26V12
0 75 4 8 12 16 20 24 28 32 36 40 44 48
AR CLK1 SP CLK 2
D ARQ 1 0 S2
91
SP
Q
10 11 00 01 S0 S1
20 I/O5
9 I7
92
0 1
R5 S3*
D ARQ 1 0 S2
106
SP
Q R4 S3*
10 11 00 01 S0 S1
19 I/O4
10 I8
107
0 1
D ARQ 1 0
119
SP S2
Q
10 11 00 01 S0 S1
18 I/O3
11 I9
120
0 1
R3 S3*
D ARQ 1 0 S2 0 1 R2 S3*
131
SP
Q
10 11 00 01 S0 S1
17 I/O2
130
12 I10
D ARQ
139
1 0 S2
SP
Q R1 S3*
10 11 00 01 S0 S1
16 I/O1
13 I11
140
0 1
D ARQ
148
10 11 00 01 S0 R0 S3* S1
1 0 S2
SP
Q
15 I/O 0
14 I12
0 1
149 0 4 8 12 16 20 24 28 32 36 40 44 48
SYNCH PRESET
* When S 3 = 1 (unprogrammed) the feedback is selected by S1. When S 3 = 0 (programmed), the feedback is the opposite of that selected by S1.
16072E-6 (concluded)
PALCE26V12 Family
2-313
AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . . . . -0.6 V to +7.0 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V Industrial (I) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC (Static) ICC (Dynamic) ICC (Dynamic) Industrial Supply Current Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Test Conditions IOH = -3.2 mA IOL = 16 mA VIN = VIH or VIL VCC = Min VIN = VIH or VIL VCC = Min 2.0 0.8 10 -10 10 -10 -30 -170 115 140 150 Min 2.4 0.4 Max Unit V V V V A A A A mA mA mA mA
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1)
Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VIN = 0 V, Outputs Open (IOUT = 0 mA) H-7/10 VCC = Max, f = 0 MHz H-7/10 VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max, f = 15 MHz H-10
Commercial Supply Current
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-314
PALCE26V12H-7/10 (Com'l), H-10 (Ind)
AMD
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 0 V VOUT = 0 V VCC = 5.0 V TA = +25C f = 1 MHz Typ 5 pF 8 Unit
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges (Note 2)
Parameter Symbol tPD tS1 tS2 tH tCO tAR tARW tARR tSPR tWL tWH fMAX Maximum Frequency (Notes 3 and 4) -7 Parameter Description Input or Feedback to Combinatorial Output Setup Time from Input or Feedback Setup Time from SP to Clock Hold Time Clock to Output Asynchronous Reset to Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width LOW HIGH External Feedback Internal Feedback (fCNT) 1/(tS + tCO) 1/(tS + tCF) 6 5 5 3.5 3.5 105.3 125 8 7.5 3.5 4.5 0 6 11 8 8 8 4 4 71.4 105 10 10 Min Max 7.5 5 5 0 9 13 Min -10 Max 10 Unit ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns
tEA tER
Input to Output Enable Using Product Term Control Input to Output Disable Using Product Term Control
Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS.
PALCE26V12H-7/10 (Com'l), H-10 (Ind)
2-315
AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . . . . -0.6 V to +7.0 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V lndustrial (I) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC (Static) ICC (Dynamic) ICC (Static) ICC (Dynamic) Industrial Supply Current Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Commerical Supply Current Test Conditions IOH = -3.2 mA IOL = 16 mA VIN = VIH or VIL VCC = Min VIN = VIH or VIL VCC = Min 2.0 0.8 10 -10 10 -10 -30 -160 105 150 130 150 Min 2.4 0.4 Max Unit V V V V A A A A mA mA mA mA mA
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VIN = 0 V, Outputs Open (IOUT = 0 mA) H-15/20 VCC = Max, f = 0 MHz VIN = 0 V, Outputs Open (IOUT = 0 mA) H-15 VCC = Max, f = 15 MHz VIN = 0 V, Outputs Open (IOUT = 0 mA) H-20 VCC = Max VIN = 0 V, Outputs Open (IOUT = 0 mA) H-20 VCC = Max, f = 15 MHz
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-316
PALCE26V12H-15/20 (Com'l, Ind)
AMD
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 0 V VOUT = 0 V VCC = 5.0 V TA = +25C f = 1 MHz 8 Typ 5 pF Unit
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges (Note 2)
Parameter Symbol tPD tS tH tCO tAR tARW tARR tSPR tWL tWH -15 Parameter Description Input or Feedback to Combinatorial Output Setup Time from Input, Feedback, or SP to Clock Hold Time Clock to Output Asynchronous Reset to Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width Maximum Frequency (Notes 3 and 4) LOW HIGH External Feedback Internal Feedback (fCNT) 1/(tS + tCO) 1/(tS + tCF) 15 15 10 8 8 50 58.8 15 15 10 0 10 20 20 20 13 10 10 40 43 20 20 Min Max 15 13 0 12 25 Min -20 Max 20 Unit ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns
fMAX
tEA tER
Input to Output Enable Using Product Term Control Input to Output Disable Using Product Term Control
Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS.
PALCE26V12H-15/20 (Com'l, Ind)
2-317
AMD
SWITCHING WAVEFORMS
Input or Feedback tS Input or Feedback VT Clock tPD Combinatorial Output VT
16072E-7
VT tH VT tCO VT
16072E-8
Registered Output
Combinatorial Output
Registered Output
Input tWH Clock tWL VT Output tER VOH - 0.5V VOL + 0.5V
VT tEA VT
16072E-10
Clock Width
16072E-9
Input to Output Disable/Enable
tARW Input Asserting Asynchronous Reset tAR Registered Outputs VT tARR Clock VT
16072E-11
VT
Input Asserting Synchronous Preset tS Clock tCO Registered Outputs tH
VT tSPR VT
VT
16072E-12
Asynchronous Reset
Synchronous Preset
Notes: 1. VT = 1.5 V 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-5 ns typical.
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PALCE26V12 Family
AMD
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1 Output R2 Test Point
CL
16072E-13
Specification tPD, tCO tEA
S1 Closed Z H: Open Z L: Closed H Z: Open L Z: Closed
CL
R1
R2 Com'l: H-15/20 Ind: H-20 390 Com'l: H-7/10 Ind: H-10/15 300
Measured Output Value 1.5 V 1.5 V H Z: VOH - 0.5 V L Z: VOL + 0.5 V
50 pF 300 5 pF
tER
PALCE26V12 Family
2-319
AMD
TYPICAL ICC CHARACTERISTICS FOR THE PALCE26V12H-7/10
VCC = 5.0 V, TA = 25C
150
125
100
ICC (mA)
75
50
25
0 0 10 20 30 40 50
16072E-14
Frequency (MHz)
The selected "typical" pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to estimate the ICC requirements for a particular design.
2-320
PALCE26V12 Family
AMD
ENDURANCE CHARACTERISTICS
The PALCE26V12 is manufactured using AMD's advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar
Symbol tDR N Parameter Min Pattern Data Retention Time Min Reprogramming Cycles
parts. As a result, the device can be erased and reprogrammed--a feature which allows 100% testing at the factory.
Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions
Min 10 20 100
Unit Years Years Cycles
PALCE26V12 Family
2-321
AMD
Bus-Friendly Inputs
The PALCE26V12H-7/10 (Com'l) and H-10/15 (Ind) inputs and I/O loop back to the input after the second stage of the input buffer. This configuration reinforces
the state of the input and pulls the voltage away from the input threshold voltage where noise can cause oscillations. For an illustration of this configuration, see below.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. C VERSION*
VCC
100 k
VCC
ESD Protection
Input
VCC
VCC
VCC
100 k
Preload Circuitry
Feedback Input
16072E-15
Output
* Device PALCE26V12H-7 PALCE26V12H-10 PALCE26V12H-15 C Rev. Letter
Topside Marking: AMD CMOS PLD's are marked on top of the package in the following manner: PALCE xxxx Datecode (4 numbers) LOT ID (3 characters) - - (Rev. Letter) The Lot ID and Rev. letter are separated by two spaces.
2-322
PALCE26V12 Family
AMD
ROBUSTNESS FEATURES
The PALCE26V12 has some unique features that make it extremely robust, especially when operating in high speed design environments. Input clamping circuitry limits negative overshoot, eliminating the possibility of
false clocking caused by subsequent ringing. A special noise filter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. B VERSION*
VCC > 50 k VCC
ESD Protection and Clamping
Programming Pins only
Programming Voltage Detection
Positive Overshoot Filter
Programming Circuitry
Typical Input
VCC
VCC
> 50 k
Provides ESD Protection and Clamping Preload Circuitry Feedback Input
16072E-16
Typical Output
*
Device PALCE26V12-15 PALCE26V12-20
Rev. Letter B
Topside Marking: AMD CMOS PLD's are marked on top of the package in the following manner: PALCE xxxx Datecode (4 numbers) LOT ID (3 characters) - - (Rev. Letter) The Lot ID and Rev. letter are separated by two spaces.
PALCE26V12 Family
2-323
AMD
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed configuration. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide
Parameter Symbol tPR tS tWL Parameter Description Power-Up Reset Time Input or Feedback Setup Time Clock Width LOW
range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: The VCC rise must be monotonic. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.
Max 1000
Unit ns
See Switching Characteristics
4V Power
VCC tPR
Registered Active-Low Output
tS
Clock
16072E-17
tWL Power-Up Reset Waveform
2-324
PALCE26V12 Family
AMD
TYPICAL THERMAL CHARACTERISTICS
Measured at 25C ambient. These parameters are not tested.
PALCE26V12
Parameter Symbol jc ja jma Typ Parameter Description Thermal impedance, junction to case Thermal impedance, junction to ambient Thermal impedance, junction to ambient with air flow 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air SKINNYDIP 19 65 59 54 50 50 PLCC 18 55 48 44 39 37 Unit C/W C/W C/W C/W C/W C/W
Plastic jc Considerations The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment.
PALCE26V12H-15/20
2-325
AMD
fMAX Parameters
The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated "fMAX external." The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated "fMAX internal". A simple internal counter is a good example of this type of design, therefore, this parameter is sometimes called "fCNT." The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated "fMAX no feedback." fMAX external and fMAX no feedback are calculated parameters. fMAX external is calculated from tS and tCO, and fMAX no feedback is calculated from tWL and tWH. fMAX internal is measured.
CLK
LOGIC
REGISTER
(SECOND CHIP)
tS
t CO
tS
fMAX External; 1/(tS + tCO) CLK CLK
LOGIC
REGISTER
LOGIC
REGISTER
tS fMAX Internal (fCNT) fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)
16072E-18
2-326
PALCE26V12 Family

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